The rapid advance of microelectronic technology is prone to scale the device dimension down in order to improve speed and reduce the cost per unit device. For example, as stated by Davari, in the reference, "B. Davari, "CMOS Technology Scaling, 0.1 .mu.m and Beyond" IEDM Tech. Dig. P.555 (1996), device speed enhancement of about 3.times., circuit density improvement of 8.times., and 20-40.times. improvement in power-delay product will be achieved by scaling the CMOS technologies down to the sub-0.1 .mu.m regime, operating in the 1V range, as compared with performance of 0.35 .mu.m devices at 3.3V.
However, as device feature size moves from submicron or even down to deep-submicron ranges, more stringent problems may arise. For example, hot carrier, punchthrough effects, mobility degradation, body effects and lithography technology issues all demand to be overcome. In addition, accompanying the with miniaturizing of the feature sizes of the devices, the vertical dimension also need to be shrunk so as to improve the device characteristics, thus the reduction in the junction depth of devices becomes critical. Nevertheless the lateral spreading resistance and contact resistance of a shallow junction are often too large and, as a result, the parasitic resistance may slow down the device speed.
In recent years, for deep-submicron region devices, a self-aligned silicided technology has attracted much attention for its practical application for example, the salicide provides not only low-sheet resistance for S/D regions and for gate electrode in MOS devices but also a very clean silicide-silicon interface. Besides, it reduces at least one mask count and no additional etching step is required other than that of the conventional silicided formation method.
However, a 0.25 .mu.m feature size of the device requires a junction depth of less than 0.1 .mu.m, and the silicidation of such a shallow source/drain junction will consume a portion of the high doping region. Thus an obstacle for the silicidation of forming such an ultra-shallow junction comes from the non-uniform silicide/silicon interface which may lead to local spiking of the junction. To prevent excessive junction leakage resulting from the silicidation process, one of the effective approaches includes forming a thinner silicide than the junction, and forming the contact silicide layer before conducting the ion implantation for junction formation.
Another critical issue associated with the feature size the MOSFET scale down and degrades significantly the device performance is electrostatic discharge (ESD). However, it is known to have a poor ESD property for the transistors with an LDD structure, which is used to prohibit the hot carrier-induced degradation in MOS devices. The ESD is easily conducted through the input/output and power lead connections into the internal devices to destroy the devices. For example, as junction depth becomes shallower, the properties of integrated circuits are easily deteriorated by the human body. The high voltage can be accidentally applied to the pins of the IC package by a person while handling, and may cause the breakdown of the gate oxide of the devices. Thus, it is imperative that a built-in preventing ESD circuitry to prevent damage to the thin gate oxide of MOS transistor is formed simultaneously with the functional transistors.
Nevertheless, the devices with shallow junctions and self-aligned silicided contacts show a negative impact on electrostatic discharge (ESD) performance than the non-silicided devices. Amerasekera et al. in "Correlating Drain Junction Scaling, Salicide Thickness, and Lateral NPN Behavior, with the ESD/EOS Performance of 0.25 .mu.M CMOS Process," IEDM Tech. Dig. (1996) P.893, investigated the relationship between the current gain .beta. of a self-biased lateral NPN (parasitic bipolar in a NMOS) transistor and the ESD performance, and found that devices with lower .beta. are observed to have lower ESD performance. Further, they also suggested that .beta. is found to be strongly influenced by the effective drain/source diffusion depth below the salicide which is determined by the implant energy as well as the amount of active diffusion consumed in silicidation. Thus, it is essential to develop a salicide process in the ULSI devices but use additional processes to block the salicide and/or to use an extra implant to make the junction deeper in the ESD protective circuitry when the fabrication of both devices is performed at the same time. A minimal influence on the ESD performance would be expected.